Sonam Fulwadhwani

M.tech. Student ( VLSI)

Dept. of ETC

Jhulelal Institute Of Technology

Nagpur,Maharashtra

fulwadhwani.sonam@gmail.com

Abstract—

System on Chip (SoC) design is becoming challenging due to its complexity and the necessity of Intellectual Properties (IP) reuse to shorten the design time. OCP (Open Core Protocol) is an efficient bus protocol for the core communication between IP blocks. Bus Bridge interconnects other bus standards to OCP.I2C is a simple bidirectional two wire bus for efficient inter IC control. This paper focuses on the implementation and design of Bus Bridge using OCP master and I2C slave protocol. Multi voltage design for power reduction is the important feature of the paper. The implementation of the developed FSMs for OCP and I2C was done in VHDL and was synthesized using Xilinx ISE 10.1 synthesis tool design compiler.

Keywords—I2C controller, OCP Bridge, OCP compliant, Master, Slave, Interface, Power reduction, Multi voltage Design.

I. Introduction

Current technology trends, scaling and with end users show a marked preference for the smaller geometries of deep sub micron processes force a design style where multiple independent circuit implementations are integrated together into a single System-On-Chip (SoC). However, contemporary SoC designs have their own share of issues and challenges. The major challenges faced by a design engineer include the ever increasing complexity in modern SoC designs, reusability, time-to-market, communication between Intellectual Property (IP) cores, integration of different clocked domain IP cores, and global clock distributions on a chip. The design of standard Network-on-Chip (NoC) interfaces to SoC is pivotal in addressing design reusability, time-to-market, and integration of IP cores employing different clock domains (synchronous, elastic, and asynchronous).

OCP is a standard core-centric protocol which addresses the IP cores reusability. This not only allows independent IP core development without IP core interconnect network but also allows IP core development in parallel with a system design, reducing design time, design risk, and manufacturing costs.OCP data communication models range from simple request grant handshaking through pipelined request–response to complex out-of order transaction. OCP describes a point-to- point interface between two communication module, such as IP cores and bus interface modules (bus wrappers).

II. OCP Compliant system

OCP’s strength is the ability to configure an interface to match a core’s communication requirements. At least one OCP interface must be included in the core for compliance. All aspects of the OCP interface specification must be complied by each  OCP interface on the core. There are 3 major types of interfaces as specified by OCP. (i) Bus Bridge Interface (ii) Processor Interface (iii) Memory Interface. The  Bus bridge  interface  includes an external bus like AXI or USB and the internal bus will be OCP. The Processor interface includes the interface between processors which include only the OCP master. These interfaces differ in protocol features or signals to optimize the needs of IP cores. Whereas, they follow the same OCP timing and validation rules, that simplifies the cost in     and implementation verification.

III.   OCP bridge interface system

To simplify the creation of bridges to other interface protocols, the bridging profiles of OCP are designed. The bridge has an OCP master or slave protocol. It is classified into  two types  (i) A simple H-bus profile which provides  a connection through an external bridge for example an AMBA AHB protocol to a CPU (ii)  The X-bus profile supports non-cacheable and cacheable instruction and data traffic between CPU and the memories and  register interfaces of other targets.

IV. The System Implemented

The need for a model to understand the OCP bus bridge compliant system and also a processor interface system, the scope of the research is extended. The design comprises the Bus Bridge system as the OCP Master and I2C controller as the OCP Slave. The Master accepts responses and gives requests whereas the Slave receives and responds to the requests provided by the master. Acknowledgments are indicated with the help of the Handshake Signals that are provided for both Master as well as the Slave. The Processor which is designed with OCP master is interfaced with the I2C controller which gives the output serial I2C buses.

The I2C controller responds to the master signal from the processor and gives the serial two wire output SDA and SCL. By switching the command field to write the master starts its write operation and presents a valid data and address. According to the Design a write is performed when the Slave accepts the command and captures data and address. The master initiates a read request by switching its command field to read. Thus it presents a valid address and the slave accepts the command. The data  from the specified address is captured by the slave and is driven to the master. This proposed system is parameterizable for both address and data.

A.  I2C Controller without OCP

In the Interface an I2C controller is designed as a Slave.The data is transferred in I2C bus synchronously to SCL on the SDA line on a byte by byte basis. For each data bit there is one SCL clock pulse with the MSB being transmitted first. Each transferred byte is followed by an acknowledgment bit. The master provides the slave address for I2C slave, the address and data to be written and read. According to the I2C bus protocol, these are the output of  I2C serial buses SDA, SCL.

TABLE  I. DESIGN PARAMETERS OF I2C CONTROLLER     

Design Parameter	Size ( in bits)
Address	8
Data	8

B. Processor without OCP

In the Interface, the Processor is the Master whose address and data are mapped to the I2C controller which gives the I2C bus protocol. A multicycle processor with 32-bit address and 32-bit data is designed as the Master that allows a functional unit to be used more than once per instruction.

TABLE  II. DESIGN PARAMETERS OF PROCESSOR

Design Parameter	Size ( in bits)
Address	32
Data	32
Instruction	32

C. OCP Compliant Processor

This processor is reconfigurable and is configured with OCP which contains the basic OCP signals and will serve as an OCP master. To transfer the command is OCP master command and this 3-bit signal indicates the type of OCP transfer the master is requesting. Depending on the direction of data flow, each non-idle command is either a read or write-type request. The slave will be either written into or read from, according to the Master command.

D. OCP Compliant Bus Bridge Interface

For the Interface, the entire system acts as an OCP-I2C bus bridge. This design presents the Peripheral profile with simple read and write whereas Generic profile with data handshaking.  

E. OCP Compliant I2C Controller

The master provides the transfer requests to which the I2C controller, which acts as the slave, responds. The I2C controller is configured which contains the basic OCP signals and will act as an OCP slave. The master receives the Sent back response signals.

V. Observations and Results On Experimentation

 A. Design Setup

The Table below gives the test set up for the implementation of the Proposed design.

TABLE  III.  SETUP SUMMARY

Design method	VHDL based behavioral modeling
Synthesis platform	Xilinx ISE 10.1

 

B. Synthesis Results

Xilinx ISE 10.1 design compiler is used to synthesize the proposed design. Xilinx ISE is a complete ECAD application that helps to design, debug and test the integrated circuits. In this design, the master, the slave and the interface were synthesized separately and then the interface without Burst transfer.

The table below shows the timing analysis of the I2C controller with and without OCP.

TABLE  IV.  TIMING ANALYSIS OF I2C CONTROLLER

Quantity	Value
Minimum period	Without OCP	2.001ns
With OCP	1.900ns
Maximum frequency	Without OCP	499.725MHz
With OCP	526.288MHz

The table below shows the timing analysis of the Processor.

TABLE  VI.  TIMING ANALYSIS OF PROCESSOR

Quantity	Value
Minimum period	Without OCP	1.061ns
With OCP	1.061ns
Minimum period	Without OCP	942.774MHz
With OCP	942.774MHz

 TABLE  VII.  TIMING ANALYSIS OF BRIDGE INTERFACE

Quantity	Value
Minimum period	Without OCP	2.217ns
With OCP	2.238ns
Maximum frequency	Without OCP	450.979MHz
With OCP	446.867MHz

On comparing the timing analysis of the designs with and without wrapper it is found that there is a little variation in the speed of operation with the use of OCP. On synthesis, it can be obtained that the device utilization is better for OCP compliant designs.

 C. Power Analysis

The modern day semi-conductor industries are focusing on the Power dissipation of the design. The components in the active area contribute the major part of power which is the Dynamic power. The advanced synthesis tools are ASIC as compared to the FPGA tools and are specific. These tools are available for different technologies. The table below shows the power consumption by various designs.

TABLE  VIII.  POWER ANALYSIS

Design	Dynamic power
Processor without OCP	843.383uW
Processor with OCP	876.514uW
I2C Controller without OCP	65.4895uW
I2C Controller  with OCP	88.019uW
Bus Bridge Interface without OCP	919.810uW
Bus Bridge Interface with OCP	962.312uW

The operating voltage of the system is 5V. There is an increase in the amount of power used with the introduction of OCP interface. This increases the hardware complexity of the design and that might be the reason for the increased power.

D. Multi-Voltage Design-Power Reduction

In today’s system-on-chip designs, Energy Efficiency has become a very important issue to be addressed. One way that lowers the power consumption is reducing the Supply Voltage. Thus, to provide flexibility in controlling the power and performance tradeoff, Multi Supply Voltage (MSV) is introduced. One of the latest ways for Power Optimization is by lowering the voltage supply and is one of the most effective ways. For dynamic power, a minor adjustment to voltage level can result in a significant reduction in power consumption, which is proportional to the square of the voltage.

VI. Conclusion

A paramerterizable and reconfigurable OCP compliant bus bridge interface and processor interface system specifically targeted to use with high speed applications has been presented in this paper. The lack of availability of a common interface that can be used with the different IP cores in a SoC design, is the primary trigger to the development of such a design. The complexity of the design is increased due to interfacing of different IP cores through different protocols in a SoC design. A common interface that supports all the needs of current day SoC design and it provides IP core reusability is required. That also would reduce the complexity of the system. OCP provides that common interface for IP core reusability.

In this paper, OCP for bus bridge is implemented. A comparison of the performance is being made of the bridge interface with and without OCP. In terms of speed and power consumption, the interface with OCP is preferable. The proposed design reduces the power consumption with a high speed and is a good alternative for any SoC design.

References                   

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