"RF LOW POWER CMOS DIFFERENTIAL VCO"
Volumn 1

“RF LOW POWER CMOS DIFFERENTIAL VCO”

Mr.Abhijeet Men

Abstract:

This paper presents a two-stage CMOS differential voltage-controlled ring oscillator (VCO).This work proposes a differential VCO design that has a wide operating frequency tuning range with low power consumption, better phase-noise performance and good linearity between the frequency and control voltage. Simulation results verify the theoretical development and address the layout design. The circuit was designed and simulated in 0.18μm TSMC CMOS technology.

1.1 INDEX TERMS CMOS, low power, low voltage, ring oscillator, voltage, and temperature (PVT) variation, switched tuning, voltage boosting, voltage-controlled oscillator (VCO)

2. INTRODUCTION

This paper describes a monolithic ring VCO based on the differential ring oscillator structure. A major advantage of modern PLL is the possibility of a widespread use of off-the-shelf IC chips. It is generally used in clock recovery of communication system and frequency synthesizer of wireless communication system. Recently, power consumption has become the main concern in modern VLSI because of the popular use of portable electronics. With the progress of VLSI technology, PLL is necessarily designed in system an a chip. For digital CMOS circuits, power consumptions can be expressed as Power α CVd2f, where V, is the supply voltage, f is the frequency of operation and C is the nodal capacitance. Low power design requires a reduction of either C or V. Capacitance is generally limited by the process, so the supply voltage becomes the only degree that we can change.

The VCO is the key component that controls the frequency of the PLL. A good VCO should have low phase noise low DC power and high frequency swing. VCO is an integral part of the PLL, clock recovery circuits and frequency synthesizers. It is used to adjust the clock frequency of the PLL, therefore; VCO catches the power consumption of the PLL. Besides, random fluctuations in the output frequency of the VCO, expressed in terms of jitter and phase noise, have a direct impact on the timing accuracy where phase alignment is required and on the signal-to-noise ratio where frequency translation is performed. In order to improve the power consumption and tuning range of PLL. The bottlenecks of ring oscillator are maybe its phase noise performance and the achievable highest frequency since the ring oscillator operates by deploying the parasitic capacitances instead of the passive components in their LC-based counterparts. Low power consumption is becoming more and more important in modem IC designs. Reducing power supply voltage is an effective way to reduce the power consumption of the circuits.

Phase locked loop (PLL) is a one of the key blocks in many electronic systems, which consists of a phase detector, low pass filter, voltage controlled oscillator(VCO) and divider as shown in Fig. below

A PLL consists of five main blocks:

  1. Phase Detector or Phase Frequency Detector (PD or PFD)
  2. Charge Pump (CP)
  3. Low Pass Filter (LPF)
  4. Voltage Controlled Oscillator (VCO)
  5. Divide by N Counter

The Phase-frequency detector detects any phase differences between the input reference signal and the feedback signal and thereafter generates an error signal. According to that error signal the Charge-pump either increases or decreases the amount of charge to the low pass filter. This charge either speeds up or slows down the voltage-controlled oscillator. The loop continues this process until the phase difference between the input reference signal and the feedback signal is zero or constant—that is the locked state. After the loop has achieved a locked state, the loop still continues in the process but the output of each component stays constant. The output signal has the same phase and/or frequency as the input reference signal. A frequency divider can be used in the feedback loop in order to synthesize a frequency that is different from that of the reference signal. Voltage controlled oscillators (VCOs) are the important block in the design of RF transceiver for generating local oscillator frequency to up convert and down convert the input signal. Oscillators generates periodic output sinusoidal signal whose overall transfer function is given as

(Y(s))/(X(s))=(H(s))/(1-H(s))

Two conditions must be simultaneously satisfied for steady oscillations

  1. The loop gain |H(jωo)| = 1.
  2. The total phase shift around the loop must be zero.

Frequency selective network is responsible for stabilizing frequency. The VCOs can be implemented by two different structures, one is a differential VCO (DVCO) and the other is a balanced VCO (BVCO). The DVCO is a conventional cross-coupled differential configuration that has been widely used due to its design simplicity and differential operation. Among CMOS BVCOs, the Colpitts BVCO is widely used. The conventional Colpitts BVCO uses only the nMOS core, and it requires a large supply current to start the oscillation.

The frequency of the oscillator must be adjustable. The local oscillator frequency must be varied in well defined steps; the output frequency of the oscillator frequency is varied with the help of the voltage then it is called as voltage controlled oscillator. In particular, for sinusoidal modulation

The output of the voltage controlled oscillator can be given as Where ωlo is the local oscillator frequency, kvco is the gain of the VCOs. Due to rigorous phase noise considerations in RF systems, VCOs incorporates passive resonators.

VCO is one of the blocks which work at the highest frequency in PLL system. The dominate power consumption block of PLL system is VCO. Low power VCO design is critical for low power PLL system. There are two types of widely used VCO: LC oscillator and ring oscillator. LC oscillator uses on chip spiral inductors and can get better phase noise performance than that of the ring oscillator. The on chip spiral inductors occupy a large chip area and the tuning range of the LC VCO is limited. The LC oscillator can only be used in high phase noise performance, narrow tuning range application, such as the wireless frequency synthesizer. Voltage controlled ring oscillator has poor phase noise performance comparing with LC VCO, but the tuning range of ring VCO is much larger than that of the LC VCO. The wide tuning range of the VCO is helpful for the PLL to overcome the process variation.

Furthermore, the chip area of the ring VCO is much smaller than that of the LC VCO. It is easy to integrate with other blocks in CMOS process. As a result, low voltage low power ring VCO is widely used in various PLL systems. In the modem 0.18 µm CMOS process, the threshold voltage of the MOS transistor is about 1 to 3 V, it is very difficult to design high performance analog circuits using conventional design methodology. Forward biasing of the bulk junction is used to reduce the threshold of the MOS transistor and improve the efficiency of the VCO. Combing with two techniques, a three stage ring VCO is proposed in this paper.

The proposed VCO is designed for a TSMC 0.18μm CMOS process, and it oscillates from 500 MHZ to 1.2 GHZ with power consumption 7 to 15 mw and area 2000 to 5000 μm^2 on a single 1 v to 3 v power supplies.

3. LITERATURE SUMMARY AND RELATED WORK

  • Luciano Severino de Paula, Eric Fabris, Sergio Bampi, Altamiro Amadeu Susin, “A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator” The circuit is implemented in 0.18 µm CMOS Process operates at frequency: 186 MHz to 1.58 GHz. The DC Supply of 1.8 V is applied and dissipates 11.38 mW of power. The Phase noise is -113.5 dBc / Hz.[1]
  • Sang_yeop Lee, Shuhei Amakawa, Noboru Ishihara, and Kazuya Masu, “Low-Phase-Noise Wide-Frequency-Range Ring-VCO-Based Scalable PLL with Sub harmonic Injection Locking in 0.18 µm CMOS”. [2]
  • A low-phase-noise ring-VCO-based PLL (frequency tuning range: 0.65-1.6 GHz ) with sub harmonic injection locking was realized (PLL area: 0.1 mm2) by adopting 0.18µm CMOS technology and combining pMOS resistive loads with a circuit for shifting bias levels; this makes the rail-to-rail range of voltages usable as control voltages.[3]
  • Hai Qi Liu, Wang Ling Goh and Liter Siek Centre for Integrated Circuits and Systems, Nanyang Technological University Singapore 639798. “1.8-v 10-ghz ring VCO design using 0.18-um CMOS technology”. [4]
  • Dongmin Park, et al, “Design techniques for low voltage VCO with wide tuning range and low sensitivity to environmental variations” The proposed VCO is implemented in 0.18µm CMOS technology and operates at 2.4 GHz. It achieves phase noise of -117 dBc/Hz at 1MHz offset and a tuning range 20% while consuming 0.365mW of power. The figure-of-merit with the tuning range is-197dBc/Hz, which is the lowest among recent state-of-the-art low-voltage VCOs. [5]
  • To-Po Wang, “A k-band low power colpitts VCO with voltage to current positive feedback network in 0.18 µm CMOS” Based on the proposed architecture, the fabricated VCO in standard 0.18 µm CMOS exhibits a 3.58% tuning range. Operating at 1.35V supply voltage, the VCO core consumes 3.3mW dc power. The measured phase noise is -110.82dBc/Hz at 1 MHz offset from 18.9 GHz oscillation frequency. [6] Haripriya Janardhan,Mahmoud Fawzy Wagdy, “Design of a 1GHz Digital PLLUsing 0.18μm CMOS Technology” in IEEE 2006 Third International Conference on Information Technology: New Generations (ITNG’06). [7] Ashish Raman, Jaya Nidhi Vashishtha and R K sarin “A RF Low Power 0.18-μm based CMOS Differential Ring Oscillator ” Proceedings of the World Congress on Engineering 2012 Vol II WCE 2012, July 4 – 6, 2012, London, U.K. [8]

4. BASIC BLOCK DIAGRAM AND DESCRIPTION:

The frequency of a conventional single-loop ring oscillator is limited by the smallest delay provided by the basic inverter delay cell. Hence, various techniques had been explored to minimize the delay per stage, and one of such methods is the feedforward or dual delay paths technique Presented in Fig. It is a block diagram of a three-stage ring oscillator that employs this technique. The basic concept of the feedforward oscillator is to add another secondary feedforward path into the loop to make the delay per stage smaller than that of the single-loop oscillators. The bold lines seen in Fig. represent the primary loop and the solid lines depict the secondary loop.

Block diagram of a three-stage ring oscillator

5. SOFTWARE USED:

  • Advanced Design System (ADS) : Is the electronic design automation software for RF and microwave and high speed digital application. It provides complete schematic capture and layout design environment.
  • TSMC : Taiwan Semiconductor Manufacturing Company, Limited is the world’s largest dedicated independent (pure-play) semiconductor foundry, with its headquarters and main operations located in the Hsinchu Science and Industrial Park in Hsinchu.
  • BSIM4

6. SIMULATION RESULTS:

 V-I CHARACTERISTICS OF NMOS.

 TRANSFER CHARACTEISTICS OF INVERTER

V-I CHARACTERISTICS OF PMOS

 VOLTAGE DIVIDER CIRCUIT / VOLTAGE REFRANCE GENERATOR

 INVERTER

 AND GATE

 CURRENT SINK

RING OSCILATOR

7. APPLICATIONS:

  1. PLL as frequency synthesizer
  2. Low voltage Low noise mixer
  3. Function generators.
  4. Voltage controlled oscillators (VCOs) are the important block in the design of RF transceiver used in various wireless devices such as

 Mobile phone and Bluetooth devices (up to 2.8 GHz)

Block Diagram of Phase Lock Loop

CONCLUSION:

The design of a wide range, low power consumption VCO is detailed in this work. In this work I am trying to improve the performance parameters of selected circuit topology [like power desipation, frequency, etc] by varying the gain and power of circuit. The vco will design for an TSMC 0.18µm CMOS process, and it oscillates from 500 MHz to 1.2 GHz with power consumption 7 to 15 mW and area 2000 to 5000 μm^2 On a single 1 v to 3 v power supply.

REFRANCES:

  1. Luciano Severino de Paula, Eric Fabris, Sergio Bampi, Altamiro Amadeu Susin, “A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator” The circuit is implemented in 0.18 µm CMOS Process operates at frequency: 186 MHz to 1.58 GHz. The DC Supply of 1.8 V is applied and dissipates 11.38 mW of power. The Phase noise is -113.5 dBc / Hz.
  2. Sang_yeop Lee, Shuhei Amakawa, Noboru Ishihara, and Kazuya Masu, “Low-Phase-Noise Wide-Frequency-Range Ring-VCO-Based Scalable PLL with Sub harmonic Injection Locking in 0.18 µm CMOS”
  3. A low-phase-noise ring-VCO-based PLL (frequency tuning range: 0.65-1.6 GHz ) with sub harmonic injection locking was realized (PLL area: 0.1 mm2) by adopting 0.18µm CMOS technology and combining pMOS resistive loads with a circuit for shifting bias levels; this makes the rail-to-rail range of voltages usable as control voltages.
  4. “1.8-V 10-Ghz Ring Vco Design Using 0.18-Urm Cmos Technology” Hai Qi Liu, Wang Ling Goh and Liter Siek Centre for Integrated Circuits and Systems, Nanyang Technological University Singapore 639798
  5. Dongmin Park, et al, “Design techniques for low voltage VCO with wide tuning range and low sensitivity to environmental variations” The proposed VCO is implemented in 0.18µm CMOS technology and operates at 2.4 GHz. It achieves phase noise of -117 dBc/Hz at 1MHz offset and a tuning range 20% while consuming 0.365mW of power. The figure-of-merit with the tuning range is-197dBc/Hz, which is the lowest among recent state-of-the-art low-voltage VCOs.
  6. To-Po Wang, “A k-band low power colpitts VCO with voltage to current positive feedback network in 0.18 µm CMOS” Based on the proposed architecture, the fabricated VCO in standard 0.18 µm CMOS exhibits a 3.58% tuning range. Operating at 1.35V supply voltage, the VCO core consumes 3.3mW dc power. The measured phase noise is -110.82dBc/Hz at 1 MHz offset from 18.9 GHz oscillation frequency.
  7. Haripriya Janardhan,Mahmoud Fawzy Wagdy, “Design of a 1GHz Digital PLLUsing 0.18μm CMOS Technology” in IEEE 2006 Third International Conference on Information Technology: New Generations (ITNG’06).
  8. Ashish Raman, Jaya Nidhi Vashishtha and R K sarin “A RF Low Power 0.18-μm based CMOS Differential Ring Oscillator ” Proceedings of the World Congress on Engineering 2012 Vol II WCE 2012, July 4 – 6, 2012, London, U.K.
  9. B .Razvi, “Design of ANALOG CMOS Integrated Circuits” McGraw- Hill,2001.
  10. Nikolay T. Tchamov, Svetozar S.Broussev, “Dual-Band LC VCO Architecture With a Fourth-Order Resonator” in IEEE Transactions on circuits and systems—II: Express Briefs, vol. 54, no. 3, March 2007.
  11. Guochi Huang, Student Member, IEEE, and Byung-Sung Kim, Member, IEEE, “Low Phase Noise Self-Switched Biasing CMOS LC Quadrature VCO” in IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 2, February 2009.
  12. Liang Dai, Member, IEEE, And Ramesh Harjani, Senior Member, “Design Of Low-Phase-Noise CMOS Ring Oscillators” IEEE Transactions On Circuits And Systems—II: Analog And Digital Signal Processing, Vol. 49, No. 5, IEEE, May 2002.
  13. Dominican Republic, “Design and Simulation Difference Types CMOS Phase Frequency Detector for high speed PLL” Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, Nov.3-5, 2004.
  14. Ali Hajimiri, Sotirios Limotyrakis, Thomas H. Lee “Phase Noise in Multi-Gigahertz CMOS Ring Oscillators” Center for Integrated Systems, Stanford, CA 94305-4070.
  15. C. m. hung and k. o. kenneth “A fully integrated 1.5V 5.5 GHz CMOS phase locked loop” IEEE j. solid state circuits,37(4): 521-525,april 200.
  16. B. DE Muertal “A 1.8 GHz highly tunable low phase noise CMOS VCO” custom integrated ckts conf, proc. IEEE, pages 585-588, 2004.
  17. S. Levantino C. Samori and v. Boccuzzi “A -94dbc/Hz @ 100khz, fully integrated 5Ghz,CMOS VCO” with 18% tuning range for Bluetooth applications. In IEEE conf, custom integrated ckts conf, 2006.
  18. Xintian Shi, Kilian Imfeld, Steve Tanner, Michael Ansorge and Pierre-André Farine “Low-Power CMOS PLL for Clock Multiplication” Published in IEEE Esscirc – Mixed Signal, High Voltage & High Power Circuits 7, 2006 which should be used for any reference to this work.

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